Efficient power estimation techniques for HW/SW systems

被引：6

作者：

Lajolo, M ^{[1
]}

Raghunathan, A ^{[1
]}

Dey, S ^{[1
]}

Lavagno, L ^{[1
]}

Sangiovanni-Vincentelli, A ^{[1
]}

机构：

[1] Politecn Torino, Turin, Italy

来源：

IEEE ALESSANDRO VOLTA MEMORIAL WORKSHOP ON LOW-POWER DESIGN, PROCEEDINGS | 1999年

关键词：

D O I：

10.1109/LPD.1999.750420

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present a power estimation framework for hardware/software System-On-Chip (SOC) designs based on concurrent and synchronized execution of a hardware simulator and an instruction set simulator. Concurrent execution of the simulators for different parts of the system is necessary to obtain accurate input and execution traces, and hence accurate power estimates. However, as in the case of hardware/software co-simulation, the communication and synchronization between the various simulators causes significant overhead. We describe two speedup techniques for addressing this issue - energy caching and power macromodeling - that present interesting accuracy vs. efficiency tradeoffs.

引用

页码：191 / 199

页数：9

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