An Efficient HW/SW Partitioning Algorithm for Power Optimization in Embedded Systems

Power is an important parameter to consider in the design of embedded systems (ES). Reducing the power consumption is particularly essential, in mobile systems and in high-performance systems. Several possibilities, at different levels of the circuit design, can be used to overcome this issue. At the system level, a variety of approaches are available to optimize the system and to meet the functional requirements. The codesign, which is composed of several steps, is one of the most used approaches. The Hardware Software Partitioning (HSP) is a key step in this process of codesign, in fact, it aims of mapping the best blocks to the hardware part and the best blocks to the software part. This paper proposes an algorithm to solve the HSP problem with the objective of minimizing the power consumption of the system, while keeping its performances in term of the execution time and the hardware cost. The proposed solution is based on Lagrangian Relaxation and Subgradient methods. Experimental results show that the proposed algorithm leads to more optimal solutions comparing to Genetic Algorithm (GA) and Simulated Annealing (SA) algorithm, especially for systems with large number of blocks.