Switching noise analysis framework for high speed logic families

Switching noise in ultra deep sub-micron designs is assuming increasing proportions due to decreased rise times, scaled features sizes and interconnect complexity. Moreover, to achieve higher frequencies the use of different logic families is explored, which contribution in terms of noise generation is not completely defined yet. In this paper we report some results from a detailed simulation sequence performed to define clearly the influence of technological parameters and of the use of different logic families with respect to noise generation. The aim is to use these informations in a developing CAD tool for switching noise free placement.