Switching noise analysis framework for high speed logic families

被引：3

作者：

Delaurenti, M ^{[1
]}

Graziano, M ^{[1
]}

Masera, G ^{[1
]}

Piccinini, G ^{[1
]}

Zamboni, M ^{[1
]}

机构：

[1] Politecn Torino, VLSI Lab, Dept Elect, I-10129 Turin, Italy

来源：

VLSI DESIGN 2001: FOURTEENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN | 2001年

关键词：

D O I：

10.1109/ICVD.2001.902711

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Switching noise in ultra deep sub-micron designs is assuming increasing proportions due to decreased rise times, scaled features sizes and interconnect complexity. Moreover, to achieve higher frequencies the use of different logic families is explored, which contribution in terms of noise generation is not completely defined yet. In this paper we report some results from a detailed simulation sequence performed to define clearly the influence of technological parameters and of the use of different logic families with respect to noise generation. The aim is to use these informations in a developing CAD tool for switching noise free placement.

引用

页码：524 / 530

页数：7

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