RT-level test point insertion for sequential circuits

Current paper presents a new, coarse-grain method for test point insertion performed at the RT-level. The method relies on inserting testability components to the RTL VHDL description of the design. The approach is based on non-classical, simplified concept of controllability and observability. The insertion takes place based on the list of uncontrollable and unobservable faults obtained by a sequential ATPG. Such interaction with an ATPG and resynthesis of the device after each test structure insertion would be very time-consuming. The proposed method solves its task with just three iterations. First, a testability analysis is carried out and controllability structures are inserted to the modules containing uncontrollable faults. Then, the circuit is resynthesized and the ATPG is run. Second, the observability structures are added to the modules, with remaining unobservable faults. Finally, after resynthesis and an ATPG run the overhead area is minimized by removing observability structures from blocks, where there was no increase in fault coverage. A synthesizable VHDL library of dedicated generic components for testability structures has been implemented. Experiments on six RTL benchmarks show the efficiency of the approach.