A cache memory prioritizing long waiting load instructions

In this paper, we propose a criticality-based cache memory system preventing long waiting load instructions from cache misses, based on the latency of load instructions to be issued. These load instructions have a high possibility that they are contained in a long dependence instruction sequence, resulting in the degradation of performance. Furthermore, as the latency of instructions waiting for their issue becomes long, these instructions occupy instruction windows for a long time. We consider that load instructions occupying instruction windows for a long time deteriorate the performance of computer systems. Such a long wait in the instruction window occurs because of deep dependence on other instructions or long memory accesses due to cache misses of other load instructions. By reducing cache misses caused by these critical load instructions, the increase of the critical path becomes preventable. Also, instruction windows can issue more instructions efficiently, and exploit more empty space to make use of instruction level parallelism, leading to the improvement of the performance of computer systems.