Design of combinatorial test algorithm for memory fault diagnosis

被引：1
|
作者：
Zhang Dayu [1 ]
Wang Yue [1 ]
Wang He [1 ]
Zhang Song [1 ]
Jiang Chengzhi [1 ]
机构：
[1] China Acad Space Technol, Beijing, Peoples R China
来源：
2018 EIGHTH INTERNATIONAL CONFERENCE ON INSTRUMENTATION AND MEASUREMENT, COMPUTER, COMMUNICATION AND CONTROL (IMCCC 2018) | 2018年
关键词：
test algorithm; fault diagnosis; memory device; high reliability field; fault mode;
D O I：
10.1109/IMCCC.2018.00231
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
The memory device used in high reliability field of aerospace needs fast fault diagnosis and location when function failure occurs, but simple function verification test can not even detect failure due to low fault coverage. The combination test algorithm designed by using different memory test algorithms for the coverage difference of fault mode is analyzed by the results of multiple iterations, sometimes the fault points can be accurately positioned and the failure analysis is completed. Based on an example of SRAM failure analysis, a design method of combined test algorithm for fault diagnosis is presented.
引用
收藏
页码：1112 / 1115
页数：4
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