Design of combinatorial test algorithm for memory fault diagnosis

The memory device used in high reliability field of aerospace needs fast fault diagnosis and location when function failure occurs, but simple function verification test can not even detect failure due to low fault coverage. The combination test algorithm designed by using different memory test algorithms for the coverage difference of fault mode is analyzed by the results of multiple iterations, sometimes the fault points can be accurately positioned and the failure analysis is completed. Based on an example of SRAM failure analysis, a design method of combined test algorithm for fault diagnosis is presented.