Design of Pipelined Parallel Turbo Decoder Using Contention Free Interleaver

The work presented in this paper details an efficient architecture of a pipelined parallel turbo decoder utilizing contention free interleaver. Pipeline technique has been applied to reduce the critical path delay associated to the add compare select Offset (ACSO) unit so as to increase the operating clock frequency. The computational core of the complex maximum a posteriori probability (MAP) decoder has been optimized to achieve the throughput requirement for the real time applications. The proposed decoder which consists of 32 MAP decoder core, achieves 1.138 Gbps data rate at a maximum clock frequency of 486 MHz when implemented in a 90 nm CMOS process with a silicon area of 13.82 mm(2). The proposed decoder can be made appropriate for low power portable devices by relaxing the throughput requirement.