Towards Single Pin Scan for Extremely Low Pin Count Test

Design-for-Testability (DFT) techniques for test cost reduction of digital circuits rely on efficient deployment of scan test through smart DUT (device under test) partitions, matching of scan test I/O needs to the DUT needs for increased scan data throughput, and optimal test pattern generation methods. The test cost is further reduced by testing multiple devices in parallel using the same set of ATE resources. As a result, the number of scan pins available in a DUT for test application is reduced. The need for managing different DUT partitions and ensuring that the scan I/O interface matches with the DUT requirements further aggravates the need for scan test pins. In this paper, a generic methodology for reduced pin count scan test is presented. Specific solutions are described for internal generation of all scan mode control signals, e.g. scan enable, clock control, X-mask control, switching between slow speed shift clock and high speed capture clock, etc., across one or more DUT partitions. It is shown how this method can ultimately lead to a single pin scan test solution. These methods have been implemented in cost sensitive SOC designs and, as a result, the scan test time has been reduced by 2x-3x over what has been achieved using other aggressive test cost reduction methods for scan compression. These methods are also independent of the specific scan compression solution used.