Enhanced reduced pin-count test for full-scan design

被引：42

作者：

Vranken, H ^{[1
]}

Waayers, T ^{[1
]}

Fleury, H ^{[1
]}

Lelouvier, D ^{[1
]}

机构：

[1] Philips Res Labs, IC Design Digital Design & Test, NL-5656 AA Eindhoven, Netherlands

来源：

INTERNATIONAL TEST CONFERENCE 2001, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/TEST.2001.966695

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents enhanced reduced pin-count test (E-RPCT) for low-cost test. E-RPCT is an extension of traditional RPCT for circuits in which a large number of digital IC pins is multiplexed for scan. The basic concept of E-RPCT is to provide access to the internal scan chains via an IEEE 1149.1 compatible boundary-scan architecture, instead of direct access via the IC pins. The boundary-scan chain performs serial/parallel conversion of test data. E-RPCT also provides EO wrap to test non-contacted pins. The paper presents E-RPCT for full-scan design, as well as for full-scan core-based design.

引用

页码：738 / 747

页数：10

共 48 条

[1] Enhanced Reduced Pin-Count Test for Full-Scan Design
Harald Vranken
Tom Waayers
Hervé Fleury
David Lelouvier
[J]. Journal of Electronic Testing, 2002, 18 : 129 - 143
[2] Enhanced reduced pin-count test for full-scan design
Vranken, H
Waayers, T
Fleury, H
Lelouvier, D
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[J]. 2015 16TH LATIN-AMERICAN TEST SYMPOSIUM (LATS), 2015,
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Ho, Tsung-Yi
[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2015, 34 (04) : 629 - 641
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[9] ATPG for dynamic burn-in test in full-scan circuits
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[J]. PROCEEDINGS OF THE 15TH ASIAN TEST SYMPOSIUM, 2006, : 75 - +
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Trung Anh Dinh
Yamashita, Shigeru
Ho, Tsung-Yi
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