ALPHA: A Novel Algorithm-Hardware Co-Design for Accelerating DNA Seed Location Filtering

被引:3
|
作者
Hameed, Fazal [1 ,2 ]
Khan, Asif Ali [1 ]
Castrillon, Jeronimo [1 ]
机构
[1] Tech Univ Dresden, Compiler Construct & Ctr Adv Elect Dresden cfaed, D-01069 Dresden, Germany
[2] Inst Space Technol IST, Islamabad 44000, Pakistan
关键词
Genomics; Sequential analysis; DNA; Memory management; Heuristic algorithms; Bioinformatics; Metadata; Genome sequencing; seed location filtering; processing-in-memory; DNA sequence alignment; GENETIC-VARIATION;
D O I
10.1109/TETC.2021.3093840
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Sequence alignment is a fundamental operation in genomic analysis where DNA fragments called reads are mapped to a long reference DNA sequence. There exist a number of (in)exact alignment algorithms with varying sensitivity for both local and global alignments, however, they are all computationally expensive. With the advent of high-throughput sequencing (HTS) technologies that generate a mammoth amount of data, there is increased pressure on improving the performance and capacity of the analysis algorithms in general and the mapping algorithms in particular. While many works focus on improving the performance of the aligner themselves, recently it has been demonstrated that restricting the mapping space for input reads and filtering out mapping positions that will result in a poor match can significantly improve the performance of the alignment operation. However, this is only true if it is guaranteed that the filtering operation can be performed significantly faster. Otherwise, it can easily outweigh the benefits of the aligner. To expedite this pre-alignment filtering, among others, the recently proposed GRIM-Filter uses highly-parallel processing-in-memory operations benefiting from light-weight computational units on the logic-in-memory layer. However, the significant amount of data transferring between the memory and logic-in-memory layers quickly becomes a performance and energy bottleneck for the memory subsystem and ultimately for the overall system. By analyzing input genomes, we found that there are unexpected data-reuse opportunities in the filtering operation. We propose an algorithm-hardware co-design that exploits the data-reuse in the seed location filtering operation and, compared to the GRIM-Filter, cuts the number of memory accesses by 22-54 percent. This reduction in memory accesses improves the overall performance and energy consumption by 19-44 and 21-49 percent, respectively.
引用
收藏
页码:1464 / 1475
页数:12
相关论文
共 50 条
  • [31] CoMN: Algorithm-Hardware Co-Design Platform for Nonvolatile Memory-Based Convolutional Neural Network Accelerators
    Han, Lixia
    Pan, Renjie
    Zhou, Zheng
    Lu, Hairuo
    Chen, Yiyang
    Yang, Haozhang
    Huang, Peng
    Sun, Guangyu
    Liu, Xiaoyan
    Kang, Jinfeng
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 43 (07) : 2043 - 2056
  • [32] ADMM-NN: An Algorithm-Hardware Co-Design Framework of DNNs Using Alternating Direction Method of Multipliers
    Ren, Ao
    Zhang, Tianyun
    Ye, Shaokai
    Li, Jiayu
    Xu, Wenyao
    Qian, Xuehai
    Lin, Xue
    Wang, Yanzhi
    [J]. TWENTY-FOURTH INTERNATIONAL CONFERENCE ON ARCHITECTURAL SUPPORT FOR PROGRAMMING LANGUAGES AND OPERATING SYSTEMS (ASPLOS XXIV), 2019, : 925 - 938
  • [33] A Novel Hardware-Software Co-Design and Implementation of the HOG Algorithm
    Ghaffari, Sina
    Soleimani, Parastoo
    Li, Kin Fun
    Capson, David W.
    [J]. SENSORS, 2020, 20 (19) : 1 - 21
  • [34] Hardware/Software Co-design for Accelerating Human Action Recognition
    Alhammami, Muhammad
    Pun, Ooi Chee
    Haw, Tan Wooi
    [J]. 2015 IEEE CONFERENCE ON SUSTAINABLE UTILIZATION AND DEVELOPMENT IN ENGINEERING AND TECHNOLOGY (CSUDET), 2015,
  • [35] Accelerating RTL Simulation with Hardware-Software Co-Design
    Elsabbagh, Fares
    Sheikhha, Shabnam
    Ying, Victor A.
    Nguyen, Quan M.
    Emer, Joel S.
    Sanchez, Daniel
    [J]. 56TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, MICRO 2023, 2023, : 153 - 166
  • [36] Algorithm-Hardware Co-Design of Real-Time Edge Detection for Deep-Space Autonomous Optical Navigation
    Xiao, Hao
    Fan, Yanming
    Ge, Fen
    Zhang, Zhang
    Cheng, Xin
    [J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2020, E103D (10) : 2047 - 2058
  • [37] Hardware/Software Co-design for Evolvable Hardware by Genetic Algorithm
    Shang, Qianyi
    Chen, Lijun
    Tong, Ruoxiong
    [J]. PROCEEDINGS OF 2020 IEEE INTERNATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE AND INFORMATION SYSTEMS (ICAIIS), 2020, : 306 - 309
  • [38] Bringing Powerful Machine-Learning Systems to Daily-Life Devices via Algorithm-Hardware Co-Design
    Lin, Yingyan
    [J]. 2020 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2020,
  • [39] HDSuper: Algorithm-Hardware Co-design for Light-weight High-quality Super-Resolution Accelerator
    Chang, Liang
    Zhao, Xin
    Fan, Dongqi
    Hu, Zhicheng
    Zhou, Jun
    [J]. 2023 60TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, DAC, 2023,
  • [40] Accelerating Database Workloads by Software-Hardware-System Co-design
    Bordawekar, Rajesh R.
    Sadoghi, Mohammad
    [J]. 2016 32ND IEEE INTERNATIONAL CONFERENCE ON DATA ENGINEERING (ICDE), 2016, : 1428 - 1431