Hardware/Software Co-design for Evolvable Hardware by Genetic Algorithm

被引：0

作者：

Shang, Qianyi ^{[1
]}

Chen, Lijun ^{[1
]}

Tong, Ruoxiong ^{[2
]}

机构：

[1] PLA Army Engn Univ, Equipment Simulat Training Ctr, Shijiazhuang, Hebei, Peoples R China

[2] PLA Army Engn Univ, Shijiazhuang, Hebei, Peoples R China

来源：

PROCEEDINGS OF 2020 IEEE INTERNATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE AND INFORMATION SYSTEMS (ICAIIS) | 2020年

基金：

中国国家自然科学基金;

关键词：

evolvable hardware; genetic algorithm; ARM processor; NIOS II processor; co-design architecture;

D O I：

10.1109/icaiis49377.2020.9194828

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

A co-design architecture for the field programmable gate array (FPGA)-based evolvable hardware (EHW) system is proposed. In this architecture, a virtual reconfigurable circuit (VRC) is configured by the genetic algorithm (GA). The VRC is implemented in FPGA, and the GA is executed by a processor. The ARM processor and the NIOS II processor are used. This architecture maintains the flexibility and scalability of the VRC. This approach also has the flexibility to change the parameters or even the GA algorithm without affecting the FPGA part. Three circuits of different degrees of complexity are used to evaluate the system. Experimental results showed that the co-design was successfully implemented. In addition, compared to the NIOS II approach, the ARM approach had the advantages regarding the evolution speed and the logic utilization.

引用

页码：306 / 309

页数：4

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