A methodology to investigate UWB digital receiver sensitivity to clock jitter

被引：0

作者：

Pelissier, M ^{[1
]}

Denis, B ^{[1
]}

Morche, D ^{[1
]}

机构：

[1] CEA, LETI, Direct Rech Technol, F-38054 Grenoble 9, France

来源：

2003 IEEE CONFERENCE ON ULTRA WIDEBAND SYSTEMS AND TECHNOLOGIES, CONFERENCE PROCEEDINGS | 2003年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Some UWB receivers, digitally oriented, sample the RF signal at a very high frequency close to 20 GHz. In that case, the phase noise and jitter performances of the clock synthesizer which controls the sampling process are crucial. This paper proposes a methodology to investigate UWB receiver sensitivity to clock jitter. First we develop jitter models in Delay Locked Loop (DLL) and Phase Locked Loop (PLL) synthesizers. These models are injected in a UWB chain in order to evaluate the sensitivity of sampling and correlation. Finally, some analytical expressions, fitting with the simulation results, are established.

引用

页码：126 / 130

页数：5

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