Clutter cancellation achievable with a digital waveform generator subjected to clock timing jitter

被引:0
|
作者
Spong, RN [1 ]
机构
[1] Lockheed Martin Corp, Naval Elect & Surveillance Syst Syracuse, Syracuse, NY 13221 USA
关键词
D O I
10.1109/RADAR.2000.851872
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
As digital-to-analog converters get ever faster and more accurate, it becomes ever more feasible to replace analog waveform generation for a transmit exciter with digital circuitry. Simple equations have been obtained which relate clutter cancellation achievable with an LFM pulse compressor to clock timing jitter variance, LFM waveform bandwidth, digital IF frequency, and the sampling frequency. Equations derived in this paper show that the clutter cancellation ratio consists only of terms which contain the standard deviation of the jitter squared, sigma(tau)(2), and terms with jitter raised to the 4th power, sigma(tau)(4). All sigma(tau)(2) terms are inversely proportional to the number of samples in the LFM waveform. The sigma(tau)(2) terms dominate when the combination of jitter, digital IF, and waveform bandwidths are low enough. All jitter sigma(tau)(4) terms are not reduced by the number of samples and do not benefit by an increase in sampling frequency. The sigma(tau)(4) terms dominate when the combination of jitter, digital IE and waveform bandwidths are too large. Clutter cancellation performance as it depends upon timing jitter is evaluated numerically for a variety of parameter values and checked by simulation. The results show that good clutter cancellation performance can be achieved with a digital waveform generator provided that the timing jitter is low enough for the digital IF and waveform bandwidth used.
引用
收藏
页码:428 / 434
页数:7
相关论文
共 16 条
  • [1] Clutter cancellation achievable with a digital waveform generator subjected to clock timing jitter
    Spong, Robert N.
    Cooper, Robert M.
    IEEE National Radar Conference - Proceedings, 2000, : 428 - 434
  • [2] Digital frequency modulation profile for low jitter spread spectrum clock generator
    Byun, S.
    Son, C. H.
    ELECTRONICS LETTERS, 2010, 46 (16) : 1108 - 1109
  • [3] Jitter simulation and measurement of an all-digital clock generator with dynamic frequency counting loop
    Chen, Pao-Lung
    PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 2554 - 2557
  • [4] Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator
    Kim, WooSeok
    Park, Jaejin
    Park, Hojin
    Jeong, Deog-Kyoon
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2014, 49 (03) : 657 - 672
  • [5] Integrated CMOS 0.15 ns digital timing generator for TDC's and clock distribution systems
    Christiansen, J.
    IEEE Transactions on Nuclear Science, 1995, 42 (4 pt 1): : 753 - 757
  • [6] AN INTEGRATED CMOS 0.15 NS DIGITAL TIMING GENERATOR FOR TDCS AND CLOCK DISTRIBUTION-SYSTEMS
    CHRISTIANSEN, J
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1995, 42 (04) : 753 - 757
  • [7] A 10ps jitter 2 clock cycle lock time CMOS digital clock generator based on and Interleaved Synchronous Mirror delay scheme
    Saeki, T
    Nakamura, H
    Shimizu, J
    1997 SYMPOSIUM ON VLSI CIRCUITS: DIGEST OF TECHNICAL PAPERS, 1997, : 109 - 110
  • [8] A low-jitter open-loop all-digital clock generator with 2 cycle lock-time
    Kim, Moo-Young
    Shin, Dongsuk
    Chae, Hyunsoo
    Ok, Sunghwa
    Kim, Chulwoo
    PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2007, : 369 - 372
  • [9] Low jitter all digital phase locked loop based clock generator for high speed system on-chip applications
    Moorthi, S.
    Meganathan, D.
    Janarthanan, D.
    Kumar, P. Praveen
    Perinbam, J. Raja Paul
    INTERNATIONAL JOURNAL OF ELECTRONICS, 2009, 96 (11) : 1183 - 1189
  • [10] A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time
    Kim, Moo-Young
    Shin, Dongsuk
    Chae, Hyunsoo
    Kim, Chulwoo
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2009, 17 (10) : 1461 - 1469