Fast simulation of interconnect-dominant circuits

As the convergence of programmable cores. memory blocks. sensors and other analog/RF circuits on systein-on-a-chip (SoC) for networking and wireless applications is striding forward swiftly, there is an increased demand for accurate circuit-level verification of SoC designs. This paper presents a new simulation method of interconnect-dominant circuits via a two-step LU matrix factorization method. By using this new method. unnecessary repetitions of arithmetic operations are avoided in circuit analysis. As a result, plenty of simulation time is saved without losing accuracy. The simulation results show that this method is much more efficient than HSPICE while simulating interconnect-dominant networks.