Area-efficient and reusable VLSI architecture of decision feedback equalizer for QAM modem

被引：0

作者：

Yu, HS ^{[1
]}

Kim, BW ^{[1
]}

Cho, YG ^{[1
]}

Cho, JD ^{[1
]}

Kim, JW ^{[1
]}

Lee, JK ^{[1
]}

Park, HC ^{[1
]}

Lee, KW ^{[1
]}

机构：

[1] Sung Kyun Kwan Univ, Dept Elect & Comp Engn, Seoul, South Korea

来源：

PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001 | 2001年

关键词：

Terms-Decision feedback equalizer; QAM; reusable VLSI implementation; FIR filter;

D O I：

10.1145/370155.370427

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, an area efficient VLSI architecture of decision feedback equalizer is derived accommodating 64/256 QAM modulators. This architecture is implemented efficiently in reusable VLSI structure using EDA tool due to its regular structure. The main idea is to employ a time-multiplexed design scheme grouping the adjacent filter taps with correlated internal dataflow and with data transfer having same processing sequence between blocks. We simulated the proposed design scheme using SYNOPSYS (TM) and SPW (TM).

引用

页码：404 / 407

页数：4

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