An efficient VLSI architecture for computing decision feedback equalizer coefficients from the channel state information

A novel algorithm and architecture for computing the optimal decision feedback equalizer (DFE) coefficients from a channel state information (CSI) estimate is present. The proposed algorithm maps well onto a linear chain of n highly pipelineable CORDIC based processing elements. It is thus well suited for VLSI implementation. Due to the very regular data flow, the number of processing elements may be reduced without sacrificing computational latency by recycling the data through a chain of less than n processing elements. The proposed architecture computes the optimal DFE coefficients of a twelve tap symbol spaced DFE suitable for HIPERLAN I in 2.7 mus and requires only 0.7 mm(2) area on a 0.35 mum CMOS process, assuming a clock frequency of 100 MHz.