A low-power 0.13μm CMOS OC-48SONET and XAUI compliant SERDES

被引：2

作者：

Wadhwa, R ^{[1
]}

Aggarwal, A ^{[1
]}

Edwards, J ^{[1
]}

Ehlert, M ^{[1
]}

Hoehn, J ^{[1
]}

Miao, G ^{[1
]}

Lakshmikumar, K ^{[1
]}

Khoury, J ^{[1
]}

机构：

[1] Multilink Technol Corp, Somerset, NJ USA

来源：

PROCEEDINGS OF THE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2003年

关键词：

D O I：

10.1109/CICC.2003.1249464

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The design of a continuous rate octal 1.0 to 3.2 Gb/s serializes/deserializer circuit that meets SONET and XAUI requirements is presented. The performance of the SERDES surpasses stringent OC-48 jitter generation and tolerance specifications. This is achieved with the use of a master-slave PLL tuning scheme and meticulous attention to layout and isolation techniques. Implemented in a 0.13 mum digital CMOS technology, the part exhibits less than 5mUI r.m.s. jitter and the 1.2 mm(2) transceiver dissipates 160mW.

引用

页码：577 / 580

页数：4

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