Finite element analysis for solder ball failures in chip scale package

被引:35
|
作者
Lee, T [1 ]
Lee, J [1 ]
Jung, I [1 ]
机构
[1] Samsung Elect Co Ltd, Package Dev Team, Suwon 449711, South Korea
关键词
D O I
10.1016/S0026-2714(98)00163-2
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The failure mechanism of solder ball connect in chip scale package (CSP) utilizing wire-bonded ball grid array was elucidated using finite element analysis in this study. The macro-micro-coupling technique was used in the current model. There exist two factors which contribute to solder ball cracking: shear stress due to thermal expansion mismatch between the package and the PCB and warpage of the package itself. This study revealed that shear stress due to the thermal expansion mismatch prevailed over warpage of the package in causing the solder ball cracking in the present type of CSP. (C) 1998 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码:1941 / 1947
页数:7
相关论文
共 50 条
  • [1] Finite element analysis for solder ball failures in chip scale package
    Lee, T
    Lee, J
    Jung, I
    PROCEEDINGS OF THE 1997 6TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS, 1997, : 39 - 43
  • [2] Finite element based solder joint fatigue life predictions for a same die size - Stacked - Chip scale - Ball grid array package
    Zahn, BA
    TWENTY SEVENTH ANNUAL IEEE/CPMT/SEMI INTERNATIONAL ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM, 2002, : 274 - 284
  • [3] Finite element analysis of thermal distributions of solder ball in flip chip ball grid array using ABAQUS
    Kar, Yap Boon
    Talik, Noor Azrina
    Sauli, Zaliman
    Fei, Jean Siow
    Retnasamy, Vithyacharan
    MICROELECTRONICS INTERNATIONAL, 2013, 30 (01) : 14 - 18
  • [4] Flip-chip package solder-underfill reliability using finite element analysis
    Lim, Nino Rigo Emil G.
    Ubando, Aristotle T.
    Gonzaga, Jeremias A.
    RESULTS IN ENGINEERING, 2024, 24
  • [5] The Experimental and Numerical Investigation on Shear Behaviour of Solder Ball in a Wafer Level Chip Scale Package
    Zhang, Ye
    Xu, Yangjian
    Liu, Yong
    Schoenberg, Andrew
    2010 PROCEEDINGS 60TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2010, : 1746 - 1751
  • [6] Eutectic solder flip chip technology for Chip Scale Package
    Takubo, C
    Hirano, N
    Doi, K
    Tazawa, H
    Hosomi, E
    Hiruta, Y
    NINETEENTH IEEE/CPMT INTERNATIONAL ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM - PROCEEDINGS, 1996 IEMT SYMPOSIUM, 1996, : 488 - 493
  • [7] Finite Element Analysis of Copper Pillar Interconnect Stress of Flip-chip Chip-Scale Package
    Afripin, Amirul
    Carpenter, Burt
    Hauck, Torsten
    2021 22ND INTERNATIONAL CONFERENCE ON THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICROELECTRONICS AND MICROSYSTEMS (EUROSIME), 2021,
  • [8] Finite Element Analysis for Reliability of Solder Joints Materials in the Embedded Package
    Cho, Seunghyun
    Ko, Youngbae
    ELECTRONIC MATERIALS LETTERS, 2019, 15 (03) : 287 - 296
  • [9] Finite Element Analysis for Reliability of Solder Joints Materials in the Embedded Package
    Seunghyun Cho
    Youngbae Ko
    Electronic Materials Letters, 2019, 15 : 287 - 296
  • [10] Ceramic chip scale package solder joint reliability
    Seyyedi, J
    Padgett, J
    SOLDERING & SURFACE MOUNT TECHNOLOGY, 2001, 13 (03) : 7 - 11