Research challenges for on-chip interconnection networks

被引：268

作者：

Owens, John D. ^{[1
]}

Dally, William J.

Ho, Ron

Jayasimha, D. N.

Keckler, Stephen W.

Peh, Li-Shiuan

机构：

[1] Univ Calif Davis, Davis, CA 95616 USA

[2] Stanford Univ, Dept Comp Sci, Stanford, CA 94305 USA

[3] Sun Microsyst Inc, Menlo Pk, CA USA

[4] Univ Texas, Austin, TX 78712 USA

来源：

IEEE MICRO | 2007年 / 27卷 / 05期

基金：

美国国家科学基金会;

关键词：

Embedded systems; Interconnection networks; Multicore architectures; Network on chip; On-chip interconnection networks; System on chip;

D O I：

10.1109/MM.2007.4378787

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

On-chip interconnection networks are rapidly becoming a key enabling technology for commodity multicore processors and SOCs common in consumer embedded systems. Last year, The National Science Foundation initiated a workshop that addressed upcoming research issues in OCIN technology, design, and implementation and set a direction for researchers in the field.

引用

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页码：96 / 108

页数：13

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