共 50 条
- [1] Resource Sharing for Verified High-Level Synthesis 2022 IEEE 30TH INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM 2022), 2022, : 39 - 44
- [2] Layout-driven resource sharing in high-level synthesis IEEE/ACM INTERNATIONAL CONFERENCE ON CAD-02, DIGEST OF TECHNICAL PAPERS, 2002, : 614 - 618
- [3] Impact of FPGA Architecture on Resource Sharing in High-Level Synthesis FPGA 12: PROCEEDINGS OF THE 2012 ACM-SIGDA INTERNATIONAL SYMPOSIUM ON FIELD PROGRAMMABLE GATE ARRAYS, 2012, : 111 - 114
- [4] Resource sharing combined with layout effects in high-level synthesis JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2006, 44 (03): : 231 - 243
- [5] Resource Sharing Combined with Layout Effects in High-Level Synthesis Journal of VLSI signal processing systems for signal, image and video technology, 2006, 44 : 231 - 243
- [6] Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level Synthesis 2012 IEEE 14TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS & 2012 IEEE 9TH INTERNATIONAL CONFERENCE ON EMBEDDED SOFTWARE AND SYSTEMS (HPCC-ICESS), 2012, : 1534 - 1540
- [7] SAT-based Scheduling Algorithm for High-level Synthesis Considering Resource Sharing 2022 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 22), 2022, : 3244 - 3248
- [8] Function-Level Module Sharing in High-Level Synthesis 2019 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2019, : 50 - 51
- [10] A heuristic for clock selection in high-level synthesis ASP-DAC/VLSI DESIGN 2002: 7TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE AND 15TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2002, : 414 - 419