Physical compact model for threshold voltage in short-channel double-gate devices

被引：0
|
作者：
Kim, K [1 ]
Fossum, JG [1 ]
Chuang, CT [1 ]
机构：
[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA
来源：
2003 IEEE INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES | 2003年
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D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Compact physics/process-based model for threshold voltage in double-gate devices is presented. Drain-induced barrier lowering and short-channel-induced barrier lowering models for double-gate and bulk-Si devices are derived. The validity and predictability of the models are demonstrated and confirmed by numerical device simulation results for extremely scaled (L-eff = 25 nm) double-gate and bulk-Si devices.
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页码：223 / 226
页数：4
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