2nd Level Reliability Drop Test Robustness for Wafer Level Packages

被引:0
|
作者
Pin, Queck Kian [1 ]
Ludwig, Heitzer [1 ]
Wei, Yong Wei [1 ]
机构
[1] Infineon Technol Malaysia Sdn Bhd, Batu Berendam 75350, Malacca, Malaysia
来源
PROCEEDINGS OF THE 2010 34TH IEEE/CPMT INTERNATIONAL ELECTRONICS MANUFACTURING TECHNOLOGY CONFERENCE (IEMT 2010) | 2011年
关键词
D O I
暂无
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
2nd level reliability performance during drop impact is critical for Wafer Level Packages (WLP). Accompanying the popularization of portable and mobile phone products, high reliability under board level drop test is a great concern to semiconductor manufacturers. A 0.4mm pitch Cu under bump metallization (UBM) type has been developed for mobile computing application. In this paper presents the impact on solder joint reliability with various approaches to achieve higher Drop Test (DT) robustness. Polymer Core solder ball, solder ball Sn1.2AgCu (additive Ni + alpha), polymer flux with SAC107 solder ball, solder ball Sn1.2Ag0.5Cu (doped), copper core solder ball, and additional 6 mu m passivation layer (poly imide) have been investigated. The test vehicles were 49 pins and 0.4mm ball pitch with Cu UBM. Ball shear test was carried out to measure the solder joint performance after reflow process and units were performed cross sectioned for IMC formation analysis. Board level drop test was performed as per JESD22-B111 test method. The drop test results showed polymer core solder ball gives the best performance which is more than 1000 drops, followed by Sn1.2Ag0.5Cu (doped) solder ball, polymer flux, additional 6um polyimide, Sn1.2AgCu (additive Ni + alpha) solder ball & copper core solder ball. It indicated the stress relaxation within IMC & strength improvement to achieve higher drop test performance for polymer core solder ball during drop test. On the other hand, copper core solder ball has the worst drop performance (66 drops) as it has rigid material (Cu) inside the ball and less solder amount that can absorb the drop impact and stress.
引用
收藏
页数:4
相关论文
共 50 条
  • [21] Board Level Reliability of Wafer Level Chip Scale Packages With Copper Post Technology
    Jacobe, April B.
    Lomibao, Pinky B.
    Jackson, John
    IEMT 2006: 31ST INTERNATIONAL CONFERENCE ON ELECTRONICS MANUFACTURING AND TECHNOLOGY, 2006, : 155 - 161
  • [22] The bumping of wafer level packages
    Whitmore, MA
    Staddon, MA
    Schake, JD
    FIFTH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, PROCEEDINGS, 2003, : 206 - 220
  • [23] 2nd level reliability investigation of a memory package using power cycling test
    Qi, Q
    1999 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS, PROCEEDINGS, 1999, 3906 : 688 - 693
  • [24] Modeling Techniques for Board Level Drop Test for a Wafer-Level Package
    Dhiman, Harpreet S.
    Fan, Xuejun
    Zhou, Tiao
    2008 INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING, VOLS 1 AND 2, 2008, : 994 - +
  • [25] SACQ Solder Board Level Reliability Evaluation and Life Prediction Model for Wafer Level Packages
    Lin, Wei
    Pham, Quan
    Baloglu, Bora
    Johnson, Michael
    2017 IEEE 67TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2017), 2017, : 1058 - 1064
  • [26] Wafer Level Reliability Characterization of 2.5D IC packages
    Jayabalan, Jayasanker
    Chinq, Jong Ming
    Chidambaram, Vivek
    Siang, Sharon Lim Pei
    Ming, Calvin Chua Hung
    Bhattacharya, Surya
    2018 IEEE 20TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2018, : 274 - 277
  • [27] Chip size packages with wafer-level ball attach and their reliability
    Cergel, L
    Wetz, L
    Keser, B
    White, J
    ASDAM '02, CONFERENCE PROCEEDINGS, 2002, : 27 - 30
  • [28] Drop impact life prediction model for wafer level chip scale packages
    Goh, KY
    Luan, JE
    Tee, TY
    PROCEEDINGS OF THE 7TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS. 1 AND 2, 2005, : 58 - 65
  • [29] Board Level Drop Test Modeling for System-in-Packages
    Amagai, Masazumi
    Yamada, Eiichi
    2009 IEEE 59TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, VOLS 1-4, 2009, : 700 - 703
  • [30] New CBGA package with improved 2nd level reliability
    Pendse, R
    Afshari, B
    Butel, N
    Leibovitz, J
    Hosoi, Y
    Shimada, M
    Maeda, K
    Maeda, M
    Yonekura, H
    50TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 2000 PROCEEDINGS, 2000, : 1189 - 1197