共 50 条
- [21] Board Level Reliability of Wafer Level Chip Scale Packages With Copper Post Technology IEMT 2006: 31ST INTERNATIONAL CONFERENCE ON ELECTRONICS MANUFACTURING AND TECHNOLOGY, 2006, : 155 - 161
- [22] The bumping of wafer level packages FIFTH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, PROCEEDINGS, 2003, : 206 - 220
- [23] 2nd level reliability investigation of a memory package using power cycling test 1999 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS, PROCEEDINGS, 1999, 3906 : 688 - 693
- [24] Modeling Techniques for Board Level Drop Test for a Wafer-Level Package 2008 INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING, VOLS 1 AND 2, 2008, : 994 - +
- [25] SACQ Solder Board Level Reliability Evaluation and Life Prediction Model for Wafer Level Packages 2017 IEEE 67TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2017), 2017, : 1058 - 1064
- [26] Wafer Level Reliability Characterization of 2.5D IC packages 2018 IEEE 20TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2018, : 274 - 277
- [27] Chip size packages with wafer-level ball attach and their reliability ASDAM '02, CONFERENCE PROCEEDINGS, 2002, : 27 - 30
- [28] Drop impact life prediction model for wafer level chip scale packages PROCEEDINGS OF THE 7TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS. 1 AND 2, 2005, : 58 - 65
- [29] Board Level Drop Test Modeling for System-in-Packages 2009 IEEE 59TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, VOLS 1-4, 2009, : 700 - 703
- [30] New CBGA package with improved 2nd level reliability 50TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 2000 PROCEEDINGS, 2000, : 1189 - 1197