A 1.1W single-chip MPEG-2 HDTV CODEC LSI for embedding in consumer-oriented mobile CODEC systems

被引：4

作者：

Iwasaki, H ^{[1
]}

Naganuma, J ^{[1
]}

Nakajima, Y ^{[1
]}

Tashiro, Y ^{[1
]}

Nakamura, K ^{[1
]}

Yoshitome, T ^{[1
]}

Onishi, T ^{[1
]}

Ikeda, M ^{[1
]}

Izuoka, T ^{[1
]}

Endo, M ^{[1
]}

机构：

[1] NTT Corp, Cyber Space Labs, Yokosuka, Kanagawa 2390847, Japan

来源：

PROCEEDINGS OF THE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2003年

关键词：

D O I：

10.1109/CICC.2003.1249385

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes a 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems, and demonstrates its flexibility and usefulness. This architecture consists of a half-duplex 720/30P encoding core, a half-duplex 10801 decoding core, an audio DSP, a RISC, and a multiplexer/de-multiplexer core with a dual-memory scheme for supplying data at high speeds. The LSI, which integrates 3.8 million transistors on a 9.7 mm x 9.7 mm die using the 0.13-mum seven-metal CMOS process, implements 720/30P encoding with 1.1 W, 10801 decoding with 0.8 W, and full-duplex 480P encoding and decoding simultaneously with 1.4 W. This LSI will make it possible for consumers to use HDTV quality equipment on a more widespread scale.

引用

页码：177 / 180

页数：4

共 22 条

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