Design and implementation of JPEG encoder IP core

被引：8

作者：

Lian, C ^{[1
]}

Chen, LG ^{[1
]}

Chang, HC ^{[1
]}

Chang, YC ^{[1
]}

机构：

[1] Natl Taiwan Univ, Dept Elect Engn, DSP, IC Design Lab, Taipei 106, Taiwan

来源：

PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001 | 2001年

关键词：

D O I：

10.1109/ASPDAC.2001.913273

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A complete, low cost baseline JPEG encoder soft IP and its chip implementation are presented in this paper. It features user-defined, run-time re-configurable quantization tables, highly modularized and fully pipelined architecture. A prototype, synthesized with COMPASS cell library. has been implemented in TSMC 0.6-mum single-poly, triple-metal process. It can run up to 40 MHz at 3.3V. This IP can be easily integrated into various application systems, such as scanner, PC camera and color FAX, etc.

引用

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页码：29 / 30

页数：2

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