Design and implementation of JPEG encoder IP core

被引：8
|
作者：
Lian, C [1 ]
Chen, LG [1 ]
Chang, HC [1 ]
Chang, YC [1 ]
机构：
[1] Natl Taiwan Univ, Dept Elect Engn, DSP, IC Design Lab, Taipei 106, Taiwan
来源：
PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001 | 2001年
关键词：
D O I：
10.1109/ASPDAC.2001.913273
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A complete, low cost baseline JPEG encoder soft IP and its chip implementation are presented in this paper. It features user-defined, run-time re-configurable quantization tables, highly modularized and fully pipelined architecture. A prototype, synthesized with COMPASS cell library. has been implemented in TSMC 0.6-mum single-poly, triple-metal process. It can run up to 40 MHz at 3.3V. This IP can be easily integrated into various application systems, such as scanner, PC camera and color FAX, etc.
引用
收藏
页码：29 / 30
页数：2
相关论文
共 50 条
  • [11] A FPGA Implementation of JPEG Baseline Encoder for Wearable Devices
    Li, Yuecheng
    Jia, Wenyan
    Luan, Bo
    Mao, Zhi-hong
    Zhang, Hong
    Sun, Mingui
    2015 41ST ANNUAL NORTHEAST BIOMEDICAL ENGINEERING CONFERENCE (NEBEC), 2015,
  • [12] A VLSI Implementation of Pipelined JPEG Encoder for Grayscale Images
    Zhang Qihui
    Chen Jianghua
    Zhang Shaohui
    Nan, Meng
    ISSCS 2009: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS,, 2009, : 165 - +
  • [13] Real-time implementation of JPEG encoder/decoder
    Czyszczon, TM
    Czernikowski, RS
    Shaaban, M
    Hsu, KW
    INPUT/OUTPUT AND IMAGING TECHNOLOGIES, 1998, 3422 : 281 - 292
  • [14] FPGA implementation of JPEG encoder architectures for wireless networks
    Scavongelli, C.
    Conti, M.
    EURASIP JOURNAL ON EMBEDDED SYSTEMS, 2016,
  • [15] A parameterized genetic algorithm IP core design and implementation
    Deliparaschos, K. M.
    Doyamis, G. C.
    Tzafestas, S. G.
    ICINCO 2007: PROCEEDINGS OF THE FOURTH INTERNATIONAL CONFERENCE ON INFORMATICS IN CONTROL, AUTOMATION AND ROBOTICS, VOL ICSO: INTELLIGENT CONTROL SYSTEMS AND OPTIMIZATION, 2007, : 417 - 423
  • [16] Design and implementation of a parameterizable LDPC decoder IP core
    Murphy, G
    Popovici, EM
    Bresnan, R
    Marnane, WP
    Fitzpatrick, P
    2004 24TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, PROCEEDINGS, VOLS 1 AND 2, 2004, : 747 - 750
  • [17] Hardware Implementation of JPEG2000 Encoder for Video Compression
    Jahaya, Bakkurudeen Ali
    Rehman, Attiq Ur
    Defilippis, Ivan
    ICIAS 2007: INTERNATIONAL CONFERENCE ON INTELLIGENT & ADVANCED SYSTEMS, VOLS 1-3, PROCEEDINGS, 2007, : 1296 - +
  • [18] Design and Implementation of IP Core of Interactive Projection Gesture Image
    Deng Yaohua
    Zheng Zhihang
    Wu Liming
    Zhang Qiaofen
    PROCEEDINGS OF THE 2015 6TH INTERNATIONAL CONFERENCE ON MANUFACTURING SCIENCE AND ENGINEERING, 2016, 32 : 1006 - 1009
  • [19] Design and implementation of reconfigurable AES IP core using FPGAs
    Xu, J
    Liu, YF
    Dai, ZB
    Sun, Y
    2005 6th International Conference on ASIC Proceedings, Books 1 and 2, 2005, : 711 - 713
  • [20] Abstract Clock-Based Design of a JPEG Encoder
    Abdallah, Adolf
    Gamatie, Abdoulaye
    Ben Atitallah, Rabie
    Dekeyser, Jean-Luc
    IEEE EMBEDDED SYSTEMS LETTERS, 2012, 4 (02) : 29 - 32
12345