Design and implementation of JPEG encoder IP core

被引：8

作者：

Lian, C ^{[1
]}

Chen, LG ^{[1
]}

Chang, HC ^{[1
]}

Chang, YC ^{[1
]}

机构：

[1] Natl Taiwan Univ, Dept Elect Engn, DSP, IC Design Lab, Taipei 106, Taiwan

来源：

PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001 | 2001年

关键词：

D O I：

10.1109/ASPDAC.2001.913273

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A complete, low cost baseline JPEG encoder soft IP and its chip implementation are presented in this paper. It features user-defined, run-time re-configurable quantization tables, highly modularized and fully pipelined architecture. A prototype, synthesized with COMPASS cell library. has been implemented in TSMC 0.6-mum single-poly, triple-metal process. It can run up to 40 MHz at 3.3V. This IP can be easily integrated into various application systems, such as scanner, PC camera and color FAX, etc.

引用

页码：29 / 30

页数：2

共 50 条

[1] Embedded JPEG encoder IP core and memory efficient preprocessing architecture for scanner
Lian, CJ
Chen, LG
Chang, HC
Chang, YC
[J]. 2000 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS: ELECTRONIC COMMUNICATION SYSTEMS, 2000, : 686 - 689
[2] Design & implementation of JPEG2000 encoder using VHDL
Wagh, Kanchan H.
Dakhole, Pravin K.
Adhau, Vinod G.
[J]. WORLD CONGRESS ON ENGINEERING 2008, VOLS I-II, 2008, : 670 - +
[3] Comparative Analysis of Physical Design Parameters for JPEG Encoder IP using OpenROAD
Bhatt, Purav
Jadhav, Shrikant
[J]. 2024 IEEE 5TH ANNUAL WORLD AI IOT CONGRESS, AIIOT 2024, 2024, : 0533 - 0539
[4] KEY OPTIMIZATION TECHNIQUES IN JPEG-LS IP CORE DESIGN
Zhang Xiaoyu Chen Xinkai Li Xiaowen Jiang Hanjun Zhang Chun Wang Zhihua(Department of Electronic Engineering
[J]. Journal of Electronics(China), 2010, 27 (01) : 94 - 98
[5] An ASIC implementation of JPEG2000 encoder
Liu, LB
Chen, N
Zhang, C
Meng, HY
Zhang, L
Wang, ZH
Chen, HY
[J]. CHINESE JOURNAL OF ELECTRONICS, 2005, 14 (04) : 603 - 608
[6] A self-reconfigurable implementation of the JPEG encoder
Tumeo, Antonino
Monchiero, Matteo
Palermo, Gianluca
Ferrandi, Fabrizio
Sciuto, Donatella
[J]. 2007 IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES, AND PROCESSORS, 2007, : 24 - 29
[7] A FPGA-based implementation of JPEG encoder
Ayadi, Wadhah
Elhamzi, Wajdi
Atri, Mohamed
[J]. 2016 SECOND INTERNATIONAL IMAGE PROCESSING, APPLICATIONS AND SYSTEMS (IPAS), 2016,
[8] Pipelined Arithmetic Encoder Design for Lossless JPEG XR Encoder
Chien, Ching-Yen
Huang, Sheng-Chieh
Pan, Chia-Ho
Fang, Ce-Min
Chen, Liang-Gee
[J]. ISCE: 2009 IEEE 13TH INTERNATIONAL SYMPOSIUM ON CONSUMER ELECTRONICS, VOLS 1 AND 2, 2009, : 859 - +
[9] A Scalable JPEG Encoder on a Many-Core Array
Abbott, Thomas
Baas, Bevan
[J]. 2023 IEEE 16TH INTERNATIONAL SYMPOSIUM ON EMBEDDED MULTICORE/MANY-CORE SYSTEMS-ON-CHIP, MCSOC, 2023, : 411 - 418
[10] The FPGA Design of JPEG-LS Image Lossless Decompression IP Core
Deng, Lihua
Huang, Zhenghua
[J]. 2015 CHINESE AUTOMATION CONGRESS (CAC), 2015, : 2199 - 2203

← 1 2 3 4 5 →