Simple Design Technique for Realizing Low-Voltage Low-Power CMOS Current Multiplier

A simple circuit design technique for the realization of compact low-voltage low-power CMOS four-quadrant analog current multiplier circuit has been suggested. It is based on the use of the square-law characteristic in the NMOS current squaring function circuit operating in the saturation region. The suggested four-quadrant current multiplier circuit is designed for implementing in TSMC 0.25-mu m CMOS technology with a low supply voltage of +/- 0.75V. To evaluate the circuit performance, the circuit has been simulated by PSPICE program. The simulation results show that the circuit has a linearity error of about 1%, a THD of 1.07% at 100 kHz, the total power consumption of 87.6 mu W and -3dB bandwidth of 1.32 GHz.