Power estimation of time variant SoCs with TAPES

During the design process of modern SoCs (systems on chip), design tools and methods are required for the exploration of promising solutions. Evaluation criteria in this process are performance and often also power consumption. The design space is expanded by a trend towards time variant SoCs, which adapt their behaviour at run time to improve reliability or power consumption. This paper presents an extension to the TAPES system simulator in order to enable not only the exploration of architectures but also the investigation of power minimization strategies. The usefulness of the simulator is demonstrated in an architecture exploration of a network processor