System level simulation of autonomic SoCs with TAPES

被引：0
|
作者：
Lankes, Andreas [1 ]
Wild, Thomas [1 ]
Zeppenfeld, Johannes [1 ]
机构：
[1] Tech Univ Munich, Inst Integrated Syst, D-8000 Munich, Germany
来源：
ARCHITECTURE OF COMPUTING SYSTEMS - ARCS 2008, PROCEEDINGS | 2008年 / 4934卷
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
During the design process of modern SoCs (systems on chip), system architects require the support of design tools and methods that allow for a precise exploration of promising solutions. A trend towards autonomic SoCs is being proposed, in which a system's behavior is adapted at run time to improve reliability or power consumption. However, this opens ever more degrees of freedom in the definition of suitable architectures. Not only must the allocation and binding of resources and tasks be determined, but also the strategies by which an autonomic system adapts to changing working conditions. This paper presents an extension to the TAPES system simulator in order to support the evaluation of autonomic SoCs.
引用
收藏
页码：9 / 22
页数：14
相关论文
共 50 条
  • [1] Power estimation of time variant SoCs with TAPES
    Lankes, Andreas
    Wild, Thomas
    Zeppenfeld, Johannes
    DSD 2007: 10TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS, 2007, : 261 - 264
  • [2] Methodology for Improved Event-Driven System-Level Simulation of an RF Transceiver Subsystem for Wireless SoCs
    Speicher, Fabian
    Beyerstedt, Christoph
    Scholl, Markus
    Saalfeld, Tobias
    Bonehi, Vahid
    Schrey, Moritz
    Wunderlich, Ralf
    Heinen, Stefan
    2018 13TH INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA (DTIS 2018), 2018,
  • [3] LEAF: A system level leakage-aware floorplanner for SoCs
    Gupta, Aseem
    Dutt, Nikil D.
    Kurdahi, Fadi J.
    Khouri, Kamal S.
    Abadir, Magdy S.
    PROCEEDINGS OF THE ASP-DAC 2007, 2007, : 274 - +
  • [4] Modeling and Simulation of System Bus and Memory Collisions in Heterogeneous SoCs
    Wang, Jooho
    Gim, Yungyu
    Park, Sungkyung
    Park, Chester Sungchung
    IEEE ACCESS, 2022, 10 : 25901 - 25921
  • [5] A Hierarchical Approach Towards System Level Static Timing Verification of SoCs
    Chakraborty, Rupsa
    Chowdhury, Dipanwita Roy
    2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 2009, : 201 - 206
  • [6] System level fault simulation
    Sanchez, P
    Hidalgo, I
    INTERNATIONAL TEST CONFERENCE 1996, PROCEEDINGS, 1996, : 732 - 740
  • [7] Computer simulation of cardiovascular system under the autonomic nervous system control
    Li, XS
    Yang, DC
    Bai, J
    IEEE-EMBS ASIA PACIFIC CONFERENCE ON BIOMEDICAL ENGINEERING - PROCEEDINGS, PTS 1 & 2, 2000, : 107 - 108
  • [8] System level virtual prototyping of DSP SOCs using grammar based approach
    Hemani, A
    Deb, AK
    Öberg, J
    Postula, A
    Lindqvist, D
    Fjellborg, B
    DESIGN AUTOMATION FOR EMBEDDED SYSTEMS, 2000, 5 (3-4) : 295 - 311
  • [9] System-Level Memory Optimization for High-Level Synthesis of Component-Based SoCs
    Pilato, Christian
    Mantovani, Paolo
    Di Guglielmo, Giuseppe
    Carloni, Luca P.
    2014 INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE CODESIGN AND SYSTEM SYNTHESIS (CODES+ISSS), 2014,
  • [10] Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test
    Almeida, F.
    Bernardi, P.
    Calabrese, D.
    Restifo, M.
    Reorda, M. Sonza
    Appello, D.
    Pollaccia, G.
    Tancorre, V.
    Ugioli, R.
    Zoppi, G.
    2019 IEEE 22ND INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS), 2019,
12345