Analyzing SEU effects in SRAM-based FPGAs

被引：6

作者：

Violante, M ^{[1
]}

Ceschia, M ^{[1
]}

Reorda, MS ^{[1
]}

Paccagnella, A ^{[1
]}

Bernardi, P ^{[1
]}

Rebaudengo, M ^{[1
]}

Bortolato, D ^{[1
]}

Bellato, M ^{[1
]}

Zambolin, P ^{[1
]}

Candelori, A ^{[1
]}

机构：

[1] Politecn Torino, I-10129 Turin, Italy

来源：

9TH IEEE INTERNATIONAL ON-LINE TESTING SYMPOSIUM, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/OLT.2003.1214377

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Commercial-Off-The-Shelf SRAM-based FPGA devices are becoming of interests for applications where high dependability and low cost are mandatory constraints. This paper proposes a new method for assessing the effects of SEUs in the device configuration memory. The method combines radiation testing for technology characterization and simulation-based fault injection for SEU propagation. Experimental results we gathered with the purpose of modeling the effects of SEUs in the FPGA configuration memory are reported and commented.

引用

页码：119 / 123

页数：5

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