共 50 条
- [1] A VLSI architecture for Joint Source-Channel Trellis Coding. 42ND MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2, 1999, : 223 - 227
- [3] A study of a suboptimal VLSI architecture for Joint Source-Channel Trellis Coding ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL I: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY, 2000, : 643 - 646
- [4] A Novel VLSI Architecture for Hybrid DCT-SVD Image Coding Algorithm JOURNAL OF ACTIVE AND PASSIVE ELECTRONIC DEVICES, 2008, 3 (02): : 143 - 152
- [5] A VLSI Architecture of the Square Root Algorithm for V-BLAST Detection Journal of VLSI signal processing systems for signal, image and video technology, 2006, 44 : 219 - 230
- [6] A VLSI architecture of the square root algorithm for V-BLAST detection JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2006, 44 (03): : 219 - 230
- [8] A VLSI architecture for video coding based on PDVQ 2007 INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS, VOLS 1 AND 2, 2007, : 240 - 243
- [9] A VLSI architecture for arithmetic coding of multilevel images IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1998, 45 (01): : 163 - 168