Maxi zing the Performance of NoC-based MPSoCs under Total Power and Power Density Constraints

This paper presents an application mapping problem, which aims to maximize the performance of NoC-based multi-processor system-on-chip (MPSoC) designs without violating the total power and power density budgets of the chip, while maintaining the routability of all communicating cores. The mapping problem also accounts for the fact that, due to process variations, speed and leakage power characteristics of cores and routers may be quite different from one another. The problem is formulated as a mixed-integer, non-linear mathematical program, and solved heuristically by a polynomial-time combinatorial algorithm. The proposed algorithm achieves 34% (31%) on average and 52% (49%) maximum performance improvement under 16nm planar CMOS (7nm FinFET) technology when mapping different applications with different number of tasks to a 64-core processor compared with the baseline algorithms.