Maxi zing the Performance of NoC-based MPSoCs under Total Power and Power Density Constraints

被引：0

作者：

Shafaei, Alireza ^{[1
]}

Wang, Yanzhi ^{[2
]}

Chen, Lizhong ^{[3
]}

Chen, Shuang ^{[1
]}

Pedram, Massoud ^{[1
]}

机构：

[1] Univ Southern Calif, Dept Elect Engn, Los Angeles, CA 90089 USA

[2] Syracuse Univ, Dept Elect Engn & Comp Sci, Syracuse, NY USA

[3] Oregon State Univ, Sch Elect Engn & Comp Sci, Corvallis, OR 97331 USA

来源：

PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN ISQED 2016 | 2016年

关键词：

MODEL;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an application mapping problem, which aims to maximize the performance of NoC-based multi-processor system-on-chip (MPSoC) designs without violating the total power and power density budgets of the chip, while maintaining the routability of all communicating cores. The mapping problem also accounts for the fact that, due to process variations, speed and leakage power characteristics of cores and routers may be quite different from one another. The problem is formulated as a mixed-integer, non-linear mathematical program, and solved heuristically by a polynomial-time combinatorial algorithm. The proposed algorithm achieves 34% (31%) on average and 52% (49%) maximum performance improvement under 16nm planar CMOS (7nm FinFET) technology when mapping different applications with different number of tasks to a 64-core processor compared with the baseline algorithms.

引用

页码：49 / 56

页数：8

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