A Low-Jitter Sub-Sampling PLL With a Sub-Sampling DLL

被引：9

作者：

Qian, Yuan Cheng ^{[1
,2
]}

Chao, Yen Yu ^{[1
,2
]}

Liu, Shen Iuan ^{[1
,2
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan

[2] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2022年 / 69卷 / 02期

关键词：

Voltage-controlled oscillator; phase-locked loop; sub-sampling; delay-locked loop; jitter; phase noise;

D O I：

10.1109/TCSII.2021.3105552

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A sub-sampling phase-locked loop (SSPLL) with a sub-sampling delay-locked loop is presented to extend the loop bandwidth and achieve the low jitter. A falling-edge tuning loop is added to align the falling edge of the reference clock with the rising one of the output clock. The proposed SSPLL is realized in a 0.18 mu m CMOS process and its active area is 0.185mm(2). At the output frequency of 2.2GHz, the proposed SSPLL achieves an in-band phase noise of -111.83dBc/Hz and -116.41dBc/Hz at 100kHz and 4MHz offset frequency respectively with a division ratio of 44. Its root-mean-square jitter integrated from 10kHz to 100MHz is 655fs. The measured reference spur is -50.3dBc.

引用

页码：269 / 273

页数：5

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