BIST architectures selection based on behavioral testing

被引：0

作者：

Biasoli, G ^{[1
]}

Ferrandi, F ^{[1
]}

Fin, A ^{[1
]}

Fummi, F ^{[1
]}

Sciuto, D ^{[1
]}

机构：

[1] Politecn Milan, Dipartimento Elettr & Informat, I-20133 Milan, Italy

来源：

IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS | 2000年

关键词：

D O I：

10.1109/DFTVS.2000.887169

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

BIST techniques have been widely explored to create the best performing self-testing architecture. Their success depends on type of test patterns required by the circuit under rest. Main goal of the paper is to show a methodology, based on behavioral information, to identify the best suited BIST architecture for it given circuit under test. LFSR-based architectures for behavioral rest sequences providing a high stuck-at-fault coverage have been explored and evaluated.

引用

页码：292 / 298

页数：7

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