Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE)

被引：9
|
作者：
Masahara, M
Matsukawa, T
Ishii, K
Liu, YX
Nagao, M
Tanoue, H
Tanii, T
Ohdomari, I
Kanemaru, S
Suzuki, E
机构：
[1] Natl Inst Adv Ind Sci & Technol, Nanoelect Res Inst, Tsukuba, Ibaraki 3058568, Japan
[2] Waseda Univ, Sch Sci & Engn, Tokyo 1698555, Japan
来源：
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS | 2003年 / 42卷 / 4B期
关键词：
vertical double-gate MOSFET; ion-bombardment retarded etching of Si; TMAH; wet etching; ion implantation; ultrathin Si wall;
D O I：
10.1143/JJAP.42.1916
中图分类号：
O59 [应用物理学];
学科分类号：
摘要：
It was found that the etch rate of Si in tetramethylammonium hydroxide (TMAH) solution is significantly retarded by introducing ion implantation damage.. By utilizing this new phenomenon, i.e., ion-bombardment-retarded etching (IBRE) of Si, a novel process to fabricate an ultrathin Si channel wall for the vertical double-gate (DG) metal-oxide-semiconductor field effect transistor (MOSFET) was developed. We succeeded in fabricating a vertical Si wall with thickness of 16 nm on bulk Si substrate with no introduction of dry etching damage. The effectiveness of thinning the Si channel wall to the characteristics of a vertical DG MOSFET was examined by means of simulations.
引用
收藏
页码：1916 / 1918
页数：3
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