What's between simulation and formal verification? (Extended abstract)

被引：0
|
作者：
Dill, DL [1 ]
机构：
[1] Stanford Univ, Stanford, CA 94305 USA
来源：
1998 DESIGN AUTOMATION CONFERENCE, PROCEEDINGS | 1998年
关键词：
D O I：
暂无
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
This embedded tutorial surveys some possibilities for verification techniques that combine conventional simulation and ideas, techniques, and algorithms from formal verification, to obtain better functional test coverage of large designs.
引用
收藏
页码：328 / 329
页数：2
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