VLSI Hardware accelerator for the MPEG-4 padding algorithm

被引:0
|
作者
Heer, C [1 ]
Migge, K [1 ]
机构
[1] Siemens AG, D-81730 Munich, Germany
来源
MEDIA PROCESSORS 1999 | 1998年 / 3655卷
关键词
MPEG-4 padding algorithm; VLSI architecture; hardware accelerator;
D O I
10.1117/12.334758
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
引用
收藏
页码:113 / 119
页数:7
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