Efficient Implementation of High Performance Read out Integrated Circuit

被引：0

作者：

Gupta, Hari Shanker ^{[1
]}

Chakrabarti, Subhananda ^{[1
]}

Baghini, Maryam Shojaei ^{[1
]}

Sharma, D. K. ^{[1
]}

Kumar, A. S. Kiran ^{[2
]}

Mehta, Sanjeev ^{[2
]}

Paul, Sandip ^{[2
]}

Chaurasia, Ravi Shankar ^{[2
]}

Roychowdhury, A. ^{[2
]}

机构：

[1] Indian Inst Technol, Dept Elect Engn, Bombay, Maharashtra, India

[2] Ctr Space Applicat, Ahmadabad, Gujarat, India

来源：

2014 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC) | 2014年

关键词：

ROIC; Fast spice; detectors; charge handling capacity;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The Read out Integrated Circuit (ROIC) consists of charge integration, charge to voltage conversion, Pixel voltage multiplexing, signal transfer and amplification stages. The control circuit manages all the sequential events from charge integration to amplification stage. Design and optimization of ROIC for hybrid detectors has multidimensional challenges including requirement for long simulation time for specified 25 to 100 Hz frame rate. Normally useful simulation data starts after 3 frame time and minimum transient simulation required for the same is 10 ms for 100 Hz frame rate. The simulation time for each input condition is similar to 120 hours with traditional simulators. ROIC critical specifications i.e. charge handling capacity and linearity has to be checked before chip integration to Pad. The linearity check requirs at least six point simulation and lead to 1 month simulation time on state of the art servers. Fast spice simulator with set_sim_level 5 has been used for the first time and reduces simulation time to 230 hours on same machine for the linearity simulation of ROIC. Test chip 4x4 ROIC has been fabricated using UMC 180 nm CMOS process and experimental results matched within 0.4% variation w.r.t. fast spice simulation results.

引用

页数：2

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