An efficient architecture for two-dimensional discrete wavelet transform

被引:111
|
作者
Wu, PC [1 ]
Chen, LG
机构
[1] Inst Informat Ind, Div Informat Technol, Taipei, Taiwan
[2] Natl Taiwan Univ, Dept Elect Engn, Taipei 10764, Taiwan
关键词
decimation filters; discrete wavelet transform; image compression; JPEG-2000; multirate digital signal processing;
D O I
10.1109/76.915359
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper proposes an efficient architecture for the two-dimensional discrete wavelet transform (2-D DWT). The proposed architecture includes a transform module, a RAM module, and a multiplexer, In the transform module, we employ the polyphase decomposition technique and the coefficient folding technique to the decimation filters of stages 1 and 2, respectively. In comparison with other 2-D DWT architectures, the advantages of the proposed architecture are 100% hardware utilization, fast computing time (0.5-0.67 times of the parallel filters'), regular data flow, and low control complexity, making this architecture suitable for next generation image compression systems, e.g., JPEG-2000.
引用
收藏
页码:536 / 545
页数:10
相关论文
共 50 条
  • [1] Efficient architecture for two-dimensional discrete wavelet transform
    Wu, Po-Cheng
    Chen, Liang-Gee
    International Symposium on VLSI Technology, Systems, and Applications, Proceedings, 1999, : 112 - 115
  • [2] An efficient VLSI architecture for two-dimensional discrete wavelet transform
    Pinto R.
    Shama K.
    International Journal of High Performance Systems Architecture, 2018, 8 (03): : 179 - 191
  • [3] An efficient architecture for two-dimensional inverse discrete wavelet transform
    Wu, PC
    Huang, CT
    Chen, LG
    2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, PROCEEDINGS, 2002, : 312 - 315
  • [4] Implementation of Efficient Architecture of Two-Dimensional Discrete Wavelet Transform
    Song, Jinook
    Park, In-Cheol
    ISOCC: 2008 INTERNATIONAL SOC DESIGN CONFERENCE, VOLS 1-3, 2008, : 701 - 702
  • [5] Efficient architecture for two-dimensional discrete wavelet transform based on lifting scheme
    Cao, Peng
    Guo, Xin
    Wang, Chao
    Li, Jie
    ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 225 - 228
  • [6] Efficient parallel architecture for lifting-based two-dimensional discrete wavelet transform
    Xiong, CY
    Tian, JW
    Liu, J
    PROCEEDINGS OF 2005 IEEE INTERNATIONAL WORKSHOP ON VLSI DESIGN AND VIDEO TECHNOLOGY, 2005, : 75 - 78
  • [7] Memory analysis and architecture for two-dimensional discrete wavelet transform
    Huang, CT
    Tseng, PC
    Chen, LG
    2004 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOL V, PROCEEDINGS: DESIGN AND IMPLEMENTATION OF SIGNAL PROCESSING SYSTEMS INDUSTRY TECHNOLOGY TRACKS MACHINE LEARNING FOR SIGNAL PROCESSING MULTIMEDIA SIGNAL PROCESSING SIGNAL PROCESSING FOR EDUCATION, 2004, : 13 - 16
  • [8] A nonseparable VLSI architecture for two-dimensional discrete periodized wavelet transform
    Hung, KC
    Hung, YS
    Huang, YJ
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2001, 9 (05) : 565 - 576
  • [9] Efficient architectures for two-dimensional discrete wavelet transform using lifting scheme
    Xiong, Chengyi
    Tian, Jinwen
    Liu, Jian
    IEEE TRANSACTIONS ON IMAGE PROCESSING, 2007, 16 (03) : 607 - 614
  • [10] An efficient architecture for lifting-based two-dimensional discrete wavelet transforms
    Barua, S
    Carletta, JE
    Kotteri, KA
    Bell, AE
    INTEGRATION-THE VLSI JOURNAL, 2005, 38 (03) : 341 - 352