Process integration of Pr-based high-k gate dielectrics

被引：4

作者：

Mane, AU ^{[1
]}

Wenger, C ^{[1
]}

Lupina, G ^{[1
]}

Schroeder, T ^{[1
]}

Lippert, G ^{[1
]}

Sorge, R ^{[1
]}

Zaumseil, P ^{[1
]}

Weidner, G ^{[1
]}

Dabrowski, J ^{[1
]}

Müssig, HJ ^{[1
]}

机构：

[1] IHP Microelect, D-15236 Frankfurt, Germany

来源：

MICROELECTRONIC ENGINEERING | 2005年 / 82卷 / 02期

关键词：

Pr2O3; Pr-silicate; wet etching; RIE; MBE; CMOS;

D O I：

10.1016/j.mee.2005.07.004

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present the process integration of the Pr-based high-k oxides Pr2O3, PrTixOy and PrxSiyOz for CMOS devices. MOS structures were grown in form of p(+) poly-Si/Pr-based dielectric/Si(100) by MBE. RIE with CF4/O-2 plasma was used to selectively remove the poly-Si layer. It was found that the Pr-based oxides layers can be dissolved with high selectivity in diluted H2SO4 solutions. Details of the etch kinetics of Pr-based oxides and poly-Si were studied. Electrical characteristics of MOS stacks with integrated PrxSiyOz are presented. (c) 2005 Elsevier B.V. All rights reserved.

引用

页码：148 / 153

页数：6

共 50 条

[41] Study of high-k gate dielectrics by means of positron annihilation
Uedono, A.
Naito, T.
Otsuka, T.
Ito, K.
Shiraishi, K.
Yamabe, K.
Miyazaki, S.
Watanabe, H.
Umezawa, N.
Hamid, A.
Chikyow, T.
Ohdaira, T.
Suzuki, R.
Ishibashi, S.
Inumiya, S.
Kamiyama, S.
Akasaka, Y.
Nara, Y.
Yamada, K.
PHYSICA STATUS SOLIDI C - CURRENT TOPICS IN SOLID STATE PHYSICS, VOL 4, NO 10, 2007, 4 (10): : 3599 - +
[42] Simulation of nanofloating gate memory with high-k stacked dielectrics
Govoreanu, B
Blomme, P
Van Houdt, J
De Meyer, K
2003 IEEE INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, 2003, : 299 - 302
[43] Transient charging and relaxation in high-k gate dielectrics and their implications
Lee, BH
Young, C
Choi, R
Sim, JH
Bersuker, G
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2005, 44 (4B): : 2415 - 2419
[44] Threshold voltage model for MOSFETs with high-K gate dielectrics
Liu, XY
Kang, JF
Sun, L
Han, RQ
Wang, YY
IEEE ELECTRON DEVICE LETTERS, 2002, 23 (05) : 270 - 272
[45] Transient charging and relaxation in high-k gate dielectrics and their implications
Lee, Byoung Hun
Young, Chadwin
Choi, Rino
Sim, Jang Hwan
Bersuker, Gennadi
Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 2005, 44 (4 B): : 2415 - 2419
[46] Charge trapping characteristics in high-k gate dielectrics on germanium
Mahata, C.
Bera, M. K.
Bose, P. K.
Maiti, C. K.
THIN SOLID FILMS, 2008, 517 (01) : 163 - 166
[47] Noise in Si and SiGe MOSFETs with high-k gate dielectrics
von Haartman, M
Malm, BG
Hellström, PE
Östling, M
NOISE AND FLUCTUATIONS, 2005, 780 : 225 - 230
[48] On the characterization of electronically active defects in high-k gate dielectrics
Buchanan, DA
Felnhofer, D
DEFECTS IN HIGH-K GATE DIELECTRIC STACKS: NANO-ELECTRONIC SEMICONDUCTOR DEVICES, 2006, 220 : 41 - +
[49] High-k Gate Dielectrics for Emerging Flexible and Stretchable Electronics
Wang, Binghao
Huang, Wei
Chi, Lifeng
Al-Hashimi, Mohammed
Marks, Tobin J.
Facchetti, Antonio
CHEMICAL REVIEWS, 2018, 118 (11) : 5690 - 5754
[50] Limiting native oxide regrowth for high-k gate dielectrics
Choi, K
Harris, H
Gangopadhyay, S
Temkin, H
COMOS FRONT-END MATERIALS AND PROCESS TECHNOLOGY, 2003, 765 : 85 - 90

← 1 2 3 4 5 →