Simultaneous multithreading trace processors

被引：0

作者：

Wang, KF ^{[1
]}

Ji, ZZ ^{[1
]}

Hu, MZ ^{[1
]}

机构：

[1] Harbin Inst Technol, Dept Comp Sci & Technol, Harbin 150001, Peoples R China

来源：

ADVANCED PARALLEL PROCESSING TECHNOLOGIES, PROCEEDINGS | 2003年 / 2834卷

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we propose a new next generation high-performance micro-architecture based on the combination of simultaneous multithreading and trace processor. By exploiting both Instruction-Level Parallelism and Thread-Level Parallelism, Simultaneous Multithreading Trace Processor can be expected to achieve higher performance than SMT or Trace Processor individual. We describe the organization of SMT Trace Processor architecture and some fundamental techniques. A path-based multiple traces prediction mechanism is also described in the paper.

引用

页码：96 / 103

页数：8

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