Fast high-level fault simulator

被引：0
|
作者：
Deniziak, S [1 ]
Sapiecha, K [1 ]
机构：
[1] Krakow Tech Univ, PL-31155 Krakow, Poland
来源：
ICECS 2004: 11TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS | 2004年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper a new fast fault simulation technique is presented for calculation fault propagation through High Level Primitives (HLPs). Reduced Ordered Ternary Decision Diagrams are used to describe HLPs. The technique is implemented in HTDD fault simulator. The simulator is evaluated with some ITC99 benchmarks. Besides high efficiency (in comparison with existing fault simulators) it shows flexibility for adoption of wide range of fault models.
引用
收藏
页码：583 / 586
页数：4
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