Design-for-testability for switched-current circuits

被引：2

作者：

Renovell, M ^{[1
]}

Azais, F ^{[1
]}

Bodin, JC ^{[1
]}

Bertrand, Y ^{[1
]}

机构：

[1] Lab Informat Robot & Microelect Montpellier, F-34392 Montpellier 5, France

来源：

16TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/VTEST.1998.670892

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper a DFT technique is proposed that provides the full controllability a,ld observability of each memory cell of a switched-current circuit. The technique is proven to be applicable to any kind of SI circuits, very easy to automate and without any impact on the circuit performances. Indeed, the hardware configuration of the circuit is presented and only the timing configuration is managed to convert the circuit into a fully testable structure in rest mode.

引用

页码：370 / 375

页数：6

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