共 50 条
- [21] Correct approximation of IEEE 754 floating-point arithmetic for program verification [J]. Constraints, 2022, 27 : 29 - 69
- [22] An FPGA Based High Speed IEEE-754 Double Precision Floating Point Multiplier U sing Verilog [J]. 2013 INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN VLSI, EMBEDDED SYSTEM, NANO ELECTRONICS AND TELECOMMUNICATION SYSTEM (ICEVENT 2013), 2013,
- [23] Software implementation of the IEEE 754R decimal floating-point arithmetic [J]. SOFTWARE AND DATA TECHNOLOGIES, 2008, 10 : 97 - 109
- [24] IEEE 754-2008 Decimal Floating-Point for Intel® Architecture Processors [J]. ARITH: 2009 19TH IEEE INTERNATIONAL SYMPOSIUM ON COMPUTER ARITHMETIC, 2009, : 225 - 228
- [25] Design and implementation of a modular and portable IEEE 754 compliant floating-point unit [J]. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS, 2006, : 1556 - +
- [26] Software implementation of the IEEE 754R decimal floating-point arithmetic [J]. ICSOFT 2006: Proceedings of the First International Conference on Software and Data Technologies, Vol 1, 2006, : 13 - 20
- [27] Implementation and Verification of IEEE-754 64-bit Floating-Point Arithmetic Library for 8-bit Soft-Core Processors [J]. 2020 8TH INTERNATIONAL ELECTRICAL ENGINEERING CONGRESS (IEECON), 2020,
- [29] A generalized floating-point quantum representation of 2-D data and their applications [J]. Quantum Information Processing, 2020, 19
- [30] RADIX CONVERSION FOR IEEE754-2008 MIXED RADIX FLOATING-POINT ARITHMETIC [J]. 2013 ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, 2013, : 1134 - 1138