A high-efficient dynamic comparator with low-offset in weak inversion region

This paper presents a novel comparator, which is operated in weak inversion to achieve the excellent energy efficiency. Detailed theoretical calculation has been given. Simulation results in a 65-nm CMOS technology match well with the theoretical analysis. This comparator achieves a high-resolution of 4 mu V at the clock frequency of 200 MHz. The power dissipation is 1.002 mu W and the offset standard deviation is about 9 mu V at 0.65 V power supply. Simulation results demonstrate the delay time is 1.304 ns for 4 mu V input difference and the Figure-of-Merit is only 3.08x10(-5) fJ/conversion-step while operating at 200 MHz. Finally, the comparator is analyzed and compared with the conventional double-tail dynamic comparator and prior art in terms of the low-power, low-offset and high-resolution.