A 1.8 to 2.4-GHz 20mW Digital-Intensive RF Sampling Receiver with a Noise-Canceling Bandpass Low-Noise Amplifier in 90nm CMOS

This paper presents a digital-intensive RF sampling receiver composed of a noise-canceling bandpass low-noise amplifier (LNA) and an RF analog-to-digital converter (ADC) for multi-band multi-mode wireless communication. The proposed LNA employs an on-chip transformer to combine the outputs of a common-gate and a common-source LNA to reduce the noise figure and enhance the linearity, while providing tunable bandpass filtering from 1.8 to 2.4-GHz. The RF ADC employs a time-based architecture that uses time-interleaved VCOs with 1st order noise shaping property, which benefits from enhanced time resolution of advanced CMOS process. A prototype chip implemented in 90 nm CMOS process has an area of 0.3 mm(2) and achieves SNR of 50 dB for 1-MHz signal bandwidth at 1.8 to 2.4-GHz carrier frequency, while consuming 20 mW from 1.2 V supply.