Built-in self-test of molecular electronics-based nanofabrics

被引:0
|
作者
Wang, ZL [1 ]
Chakrabarty, K [1 ]
机构
[1] Duke Univ, Dept Elect & Comp Engn, Durham, NC 27708 USA
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We propose a built-in self-test (BIST) procedure for nanofabrics based on chemically-assembled electronic nanotechnology. We also present a recovery procedure through which we can identify defect-free nanoblocks and switchblocks in the nanofabric under test. The proposed BIST and recovery procedures are based on the reconfiguration of the nanofabric to achieve complete fault coverage of different types of faults. We show that a large fraction of defect-free blocks can be recovered using a small number of BIST configurations. The proposed BIST procedure is well suited for regular and dense architectures that have high defect densities.
引用
收藏
页码:168 / 173
页数:6
相关论文
共 50 条
  • [31] Fully Deterministic Storage Based Logic Built-In Self-Test
    Gopalsamy, Subashini
    Pomeranz, Irith
    2023 IEEE 41ST VLSI TEST SYMPOSIUM, VTS, 2023,
  • [32] Optimization of the store-and-generate based built-in self-test
    Ubar, R.
    Jervan, G.
    Kruus, H.
    Orasson, E.
    Aleksejev, I.
    2006 INTERNATIONAL BALTIC ELECTRONICS CONFERENCE, PROCEEDINGS, 2006, : 199 - +
  • [33] Processor-based built-in self-test for embedded DRAM
    IBM Microelectronics Div, Essex Junction, United States
    IEEE J Solid State Circuits, 11 (1731-1740):
  • [34] TEST SCHEDULING AND CONTROL FOR VLSI BUILT-IN SELF-TEST
    CRAIG, GL
    KIME, CR
    SALUJA, KK
    IEEE TRANSACTIONS ON COMPUTERS, 1988, 37 (09) : 1099 - 1109
  • [35] RMBITP: a reconfigurable matrix based built-in self-test processor
    VLSI Technology, Richardson, United States
    Microelectron J, 2 (115-127):
  • [36] REALISTIC BUILT-IN SELF-TEST FOR STATIC RAMS
    DEKKER, R
    BEENKER, F
    THIJSSEN, L
    IEEE DESIGN & TEST OF COMPUTERS, 1989, 6 (01): : 26 - 34
  • [37] Built-in self-test methodology for A/D converters
    deVries, R
    Zwemstra, T
    Bruls, EMJG
    Regtien, PPL
    EUROPEAN DESIGN & TEST CONFERENCE - ED&TC 97, PROCEEDINGS, 1997, : 353 - 358
  • [38] Integration of partial scan and built-in self-test
    AT&T Bell Lab, Princeton, United States
    Journal of Electronic Testing: Theory and Applications (JETTA), 1995, 7 (1-2): : 125 - 137
  • [39] Built-in self-test for embedded voltage regulator
    Shi, Jiang
    Smith, Ricky
    DELTA 2008: FOURTH IEEE INTERNATIONAL SYMPOSIUM ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, PROCEEDINGS, 2008, : 133 - 136
  • [40] IMPLEMENTING A BUILT-IN SELF-TEST PLA DESIGN
    TREUER, R
    FUJIWARA, H
    AGARWAL, VK
    IEEE DESIGN & TEST OF COMPUTERS, 1985, 2 (02): : 37 - 48